This invention relates to a digital phase-locked loop (PLL) which responds to a square-wave input signal having an expected frequency f.sub.E and comprises a change-over switch which is switched in response to square-wave signals of different frequencies and precedes a main divider operating with a divisor D which produces the output signal of the phase-locked loop, the change-over switch being activated in dependence upon said output signal and the input signal.
A known phase-locked loop of this type, which is built in the IC MN6163 by the Firm Matsushita, comprises a change-over switch which switches between two input frequencies, one of which is derived by dividing down the other. An exclusive-OR comparison, in dependence upon how the change-over switch is switched between the two input frequencies, is performed between the signal to which the PLL should respond and the output signal of the circuit. During the periods when the two signals simultaneously have a low level or simultaneously have a high level, there is a switch to the first frequency and during the other periods there is a switch to the second frequency. This circuit has the particular drawback that the leading edges of the pulses of the output signal of the circuit are not adjusted symmetrically with respect to the pulses of the input signal. Moreover, the phase relation between these two signals is subjected to a phase jitter. The phase relation also depends on the pulse width of the signals, because the two signals are constantly compared, in response to which the change-over switch is activated. Since a phase comparison is performed all the time, the circuit has a relatively large capture-and-hold range, which is undesirable for many purposes.